ASIC Library Characterization

  • Characterize standard cells and analog-mixed signal IP for timing, power, and noise
  • Characterize SRAM and ROM IP for timing, power and noise
  • Develop and maintain DFT views and Verilog models for IP (SRAM, ROM) blocks
  • Create and validate constraints for analog/mixed-signal IP (ADC, DAC, PLL, SERDES, LDO, Bandgap etc.)
  • Automate library characterization flows using scripting languages (Use Tcl scripting to automate the characterization flow)
  • Collaborate with the design team to integrate libraries into full-chip flows (Hands on experience working with digital team for optimizing characterization data and aspect ratio of in LEF file to meet placement requirement)
  • Debug and resolve issues in timing, power, and abstraction views -> When the .lib/.lef/UPF/models for an IP don’t behave correctly in STA, power analysis, or simulation, I am the one who finds the root cause and fixes the views and models
  • Ensure high-quality deliverables for tape-out readiness -> It is make sure by rigorously validating all timing, power, physical, and behavioral views across corners and tool flows. This includes cross-checking Liberty, LEF, Verilog, UPF (Unified Power Format), and DFT models against transistor-level simulations and layout to guarantee consistency and sign-off accuracy. Additionally, ensure that all documentation, checklists, IP collateral, and integration guidelines are complete, verified, and aligned with foundry and SoC requirements to enable a smooth and error-free tape-out.
Contact Us