SRAM

Why Sicorex SRAM
  • Proven 6T bit-cell with read/write margin optimization
  • Compiler-generated macros: 1 Kb – multi-Mb, single/dual-port
  • Low-power modes (light/deep sleep), body-bias options
  • ECC-ready interfaces (SEC-DED), BIST hooks
Request Compiler Options
SRAM IP

High-performance, low-leakage 6T SRAM macros and compilers for caches, scratchpads, and AI on-chip memories.
450 nm – 55 nm · −40 °C to 165 °C · AEC-Q100 Ready

Integration Options
  • AXI/APB/AHB wrappers; cacheline / burst support
  • Corner-based .lib (timing/power/noise), Verilog, LEF/GDS
  • Redundancy (spare rows/cols), power-gating rails
  • Test collateral: MBIST, at-speed vectors, SDF back-annotation